Method for Implementing Timing Point Engineering Change Orders in an Integrated Circuit Design Flow

摘要

A method and system for automatically implementing engineering change order (ECO) corrections in an integrated circuit (IC) include a design tool performing a timing analysis on a netlist of the IC. The method may also include annotating each of the device cells with a worst timing slack through a respective timing point associated with the device cell. In addition, the method may include generating an ECO list of device cells needing ECO correction and prioritizing the ECO correction order of the device cells in the ECO list based upon cell attributes. The method may further include excluding device cells in the ECO list based upon the fan-in or fan-out connection path of other device cells in the ECO list that will be corrected, and the design tool selecting and replacing device cells in the ECO list with different device cells from a design library.