发明名称 RADIX-8 FIXED-POINT FFT LOGIC CIRCUIT CHARACTERIZED BY PRESERVATION OF SQUARE ROOT-i OPERATION
摘要 A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.
申请公布号 US2012143936(A1) 申请公布日期 2012.06.07
申请号 US201113300710 申请日期 2011.11.21
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 KATAYAMA YASUNAO;TAKANO KOHJI
分类号 G06F17/14 主分类号 G06F17/14
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