| 摘要 |
A mechanism for detection and measurement of hardware-based processor latency is disclosed. A method of the invention includes issuing an instruction to stop all running instructions on one or more processors of a multi-core computing device, starting a latency measurement code loop on each of the one or more processors, wherein for each of the one or more processors the latency measurement code loop operates to sample a time stamp counter (TSC) for a first time reading and sample the TSC for a second time reading after a predetermined period of time, and determine whether a difference between the first and the second time readings represents a discontinuous time interval where an operating system (OS) of the computing device does not control the one or more processors.
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