发明名称 SYSTEM-LEVEL EMULATION/VERIFICATION SYSTEM AND SYSTEM-LEVEL EMULATION/VERIFICATION METHOD
摘要 A system-level emulation/verification system includes an operating device for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, executing a simulation corresponding to the SOC design module, and using a transactor to interact with the simulator via an Application Programming Interface (API); and a hard-wired based platform, including a hard IP corresponding to a soft IP of the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting of the SOC design module, and outputs an operating result of the hard IP corresponding to the setting of the SOC design module. The hard-wired based platform executes an IP model proxy for receiving an output of the transactor, transmitting the output to the hard-wired platform for controlling the operation of the hard IP, and transmitting the operating result to the transactor executed by the operating device.
申请公布号 US2012143583(A1) 申请公布日期 2012.06.07
申请号 US20100960532 申请日期 2010.12.05
申请人 HUANG CHENG-YEN;CHEN CHENG-CHIEN 发明人 HUANG CHENG-YEN;CHEN CHENG-CHIEN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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