发明名称 |
METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR BY POWERING DOWN AN INSTRUCTION FETCH UNIT |
摘要 |
An apparatus and method are described for reducing power consumption in a processor by powering down an instruction fetch unit. For example, one embodiment of a method comprises: detecting a branch, the branch having addressing information associated therewith; comparing the addressing information with entries in an instruction prefetch buffer to determine whether an executable instruction loop exists within the prefetch buffer; wherein if an instruction loop is detected as a result of the comparison, then powering down an instruction fetch unit and/or components thereof; and streaming instructions directly from the prefetch buffer until a clearing condition is detected. |
申请公布号 |
WO2012040664(A3) |
申请公布日期 |
2012.06.07 |
申请号 |
WO2011US53152 |
申请日期 |
2011.09.23 |
申请人 |
INTEL CORPORATION;MADDURI, VENKATESWARA, R. |
发明人 |
MADDURI, VENKATESWARA, R. |
分类号 |
G06F1/32;G06F9/06;G06F9/30 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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