| 摘要 |
<P>PROBLEM TO BE SOLVED: To generate local signals to be supplied to a reception mixer without using a PLL circuit, which has a problem with responsiveness. <P>SOLUTION: An integrated circuit comprises a reception mixer 2 and a signal generator 3. A multistage delay circuit 32 generates a plurality of clock pulses tap 0,1-8 in response to an RF received carrier signal. A phase detection section 33 detects differences in voltage level between a particular clock pulse tap 8 and a predetermined number of previously generated clock pulses tap 0,1-7 to detect a predetermined phase of 180° of the particular clock pulse. A selector 341 of a clock generation section 34 outputs a plurality of selected clock pulse signals tap 0,2,4,6 having a plurality of phases of 0°, 45°, 90°, 135°, respectively, out of the plurality of clock pulse signals. First signal synthesis logic circuits 342, 343 perform logical operations, EX-OR, on the plurality of selected clock pulses to generate local signals LO_I,Q to be supplied to the reception mixer 2, respectively. <P>COPYRIGHT: (C)2012,JPO&INPIT |
