发明名称 PROCESSOR AND SEMICONDUCTOR DEVICE
摘要 According to embodiments, a CPU includes an address decoder configured to control input of data from a JTAG I/F and output of data to the JTAG I/F, an authentication unit configured to perform predetermined authentication processing using an entered password and a predetermined key and, if the authentication is successful, output a predetermined authentication signal, and a selector configured to control output of data to be outputted to JTAG I/F according to presence or absence of the predetermined authentication signal.
申请公布号 US2012144477(A1) 申请公布日期 2012.06.07
申请号 US201113207606 申请日期 2011.08.11
申请人 KATAYAMA ISAO;KABUSHIKI KAISHA TOSHIBA 发明人 KATAYAMA ISAO
分类号 H04L9/32;G06F21/00 主分类号 H04L9/32
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