Automated Extraction of Size-Dependent Layout Parameters for Transistor Models

摘要

A system and method for determining transistor model parameters that account for layout-dependent features in the transistor being modeled, and also in neighboring devices in the same integrated circuit. A computer-readable expression of the integrated circuit layout is retrieved, and active and gate layers in that expression extracted. For a transistor being modeled, its active regions are analyzed to determine whether these regions have a complex shape. Model parameters are derived based on volume effects of the complex shaped active regions. Neighboring active regions that affect parameters of the transistor being modeled are also identified and their effective depth determined. Strain effects due to complex shaped active regions and neighboring elements are thus included in the transistor model.