发明名称 Retention voltage generation
摘要 An integrated circuit and method are provided, the integrated circuit comprising retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage at a retention voltage node. Functional circuitry is connected between the retention voltage node and a reference voltage node, the functional circuitry being held in a data retention state when at least a minimum voltage is provided between the retention voltage node and the reference voltage node. Each of the functional circuitry and the retention voltage generation circuitry comprise at least one p-type threshold device and at least one n-type threshold device, the p-type threshold devices and the n-type threshold devices respectively having a characteristic threshold voltage and the at least one p-type threshold device and the at least one n-type threshold device in the retention voltage generation circuitry being connected in parallel between the supply voltage node and the retention voltage node. A variation in the characteristic threshold voltage of either the at least one p-type threshold device or the at least one n-type threshold device in the functional circuitry is accompanied by a corresponding variation in the characteristic threshold voltage of either the at least one p-type threshold device or the at least one n-type threshold device respectively in the retention voltage generation circuitry, thus maintaining at least the minimum voltage between the retention voltage node and the reference voltage node and thus keeping the functional circuitry in the data retention state.
申请公布号 US2012140585(A1) 申请公布日期 2012.06.07
申请号 US20100926650 申请日期 2010.12.01
申请人 VAN WINKELHOFF NICOLAAS KLARINUS JOHANNES;RICAVY SABASTIEN NICOLAS;ARM LIMITED 发明人 VAN WINKELHOFF NICOLAAS KLARINUS JOHANNES;RICAVY SABASTIEN NICOLAS
分类号 G11C5/14;G05F1/10 主分类号 G11C5/14
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