| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a frequency monitoring circuit that can implement more appropriately stable frequency monitoring. <P>SOLUTION: A watchdog timer circuit 16 includes: a charge/discharge section 161 for charging/discharging a capacitor C; a comparison section 162 for comparing a charge voltage VC with reference voltages Va-Vc to generate comparison signals Sa-Sc; a reset output section 163 for outputting a reset signal S2 depending on a frequency monitoring result of a clock signal CLK; and a control section 164 for controlling the charge/discharge section 161 and the reset output section 163 on the basis of the clock signal CLK and the comparison signals Sa-Sc. The comparison section 162 includes, as the reference voltages Va-Vc, an intermediate voltage Vc as well as an upper limit voltage Va and a lower limit voltage Vb. The control section 164 determines a logical level of the reset signal S2 in accordance with not only the results of comparison of the charge voltage VC with the upper limit voltage Va and lower limit voltage Vb but also the result of comparison of the charge voltage VC with the intermediate voltage Vc in the advent of a pulse edge of the clock signal CLK. <P>COPYRIGHT: (C)2012,JPO&INPIT |
