发明名称 |
Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics |
摘要 |
The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. |
申请公布号 |
US8193051(B2) |
申请公布日期 |
2012.06.05 |
申请号 |
US201113047172 |
申请日期 |
2011.03.14 |
申请人 |
BOJARCZUK, JR. NESTOR A.;CABRAL, JR. CYRIL;CARTIER EDUARD A.;COPEL MATTHEW W.;FRANK MARTIN M.;GOUSEV EVGENI P.;GUHA SUPRATIK;JAMMY RAJARAO;NARAYANAN VIJAY;PARUCHURI VAMSI K.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOJARCZUK, JR. NESTOR A.;CABRAL, JR. CYRIL;CARTIER EDUARD A.;COPEL MATTHEW W.;FRANK MARTIN M.;GOUSEV EVGENI P.;GUHA SUPRATIK;JAMMY RAJARAO;NARAYANAN VIJAY;PARUCHURI VAMSI K. |
分类号 |
H01L21/8238;H01L21/28;H01L29/49;H01L29/51;H01L31/113;H01L31/119 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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