发明名称 Handling multi-cycle integer operations for a multi-threaded processor
摘要 Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.
申请公布号 US8195919(B1) 申请公布日期 2012.06.05
申请号 US20070927177 申请日期 2007.10.29
申请人 OLSON CHRISTOPHER H.;GOLLA ROBERT T.;SHAH MANISH;BROOKS JEFFREY S.;ORACLE AMERICA, INC. 发明人 OLSON CHRISTOPHER H.;GOLLA ROBERT T.;SHAH MANISH;BROOKS JEFFREY S.
分类号 G06F13/00 主分类号 G06F13/00
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