发明名称 |
Correlating instruction sequences with CPU performance events to improve software performance |
摘要 |
A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern.
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申请公布号 |
US8195583(B2) |
申请公布日期 |
2012.06.05 |
申请号 |
US20090472820 |
申请日期 |
2009.05.27 |
申请人 |
FROST GARY R.;ADVANCED MICRO DEVICES, INC. |
发明人 |
FROST GARY R. |
分类号 |
G06F15/18 |
主分类号 |
G06F15/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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