发明名称 Method and computer unit for error detection and logging in a memory
摘要 In a method for detecting errors in computer data in a memory, a check sum is calculated in runtime and compared to a stored check sum. In this method, the computer data is being subdivided into at least two logical blocks and a check sum is calculated for each logical block. Also provided is a computer unit having a processor and a memory which has a ROM in which firmware is stored, and/or which has a RAM, the memory having at least two logging functions for logging established memory errors, e.g., errors in the ROM and/or the RAM.
申请公布号 US8196026(B2) 申请公布日期 2012.06.05
申请号 US20060887664 申请日期 2006.04.12
申请人 NAGARAJ NARAYANA;ROBERT BOSCH GMBH 发明人 NAGARAJ NARAYANA
分类号 G06F11/10;H03M13/00 主分类号 G06F11/10
代理机构 代理人
主权项
地址