发明名称 REDUCTION OF POWER CONSUMPTION FOR DATA ERROR ANALYSIS
摘要 A controller (e.g., a memory controller) includes initial error analysis logic (e.g., a section of a Reed Solomon or BCH codeword decoder) that determines an error count for a data element. The data element may be data stored in the memory of a memory device (e.g., a flash memory device) that incorporates the controller. Comparison logic in the controller determines when the error count exceeds a power control threshold. When the error count exceeds the power control threshold, control logic in the controller reduces the operational speed of subsequent error analysis logic (e.g., a different section of the Reed Solomon or BCH codeword decoder) for the data element. For example, the subsequent error analysis logic may be error locator logic, such as Chien search logic, that determines where the errors exist in the data element.
申请公布号 US2012137152(A1) 申请公布日期 2012.05.31
申请号 US201113313669 申请日期 2011.12.07
申请人 DROR ITAI;BERGER ALEXANDER;MOSTOVOY MICHAEL;WEINBERG YOAV 发明人 DROR ITAI;BERGER ALEXANDER;MOSTOVOY MICHAEL;WEINBERG YOAV
分类号 G06F1/32;G06F11/00 主分类号 G06F1/32
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