发明名称 SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE
摘要 A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
申请公布号 US2012135564(A1) 申请公布日期 2012.05.31
申请号 US201213361057 申请日期 2012.01.30
申请人 FAROOQ MUKTA G.;MELVILLE IAN D.;PETRARCA KEVIN S.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 FAROOQ MUKTA G.;MELVILLE IAN D.;PETRARCA KEVIN S.
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
主权项
地址