| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve the efficiency of instruction execution by accurately determining the presence/absence of register interference with respect to instructions whose data word length is different, and appropriately adjusting the issue timing of the following instruction in a vector processing circuit. <P>SOLUTION: In the vector processing circuit, each pipeline arithmetic unit is configured to perform an arithmetic operation to a plurality of array element data designated as a source in a plurality of cycles with respect to one instruction, and to store arithmetic results in a plurality of array elements designated as destinations in a plurality of cycles, and an instruction issue control circuit is configured to change the data size of the array elements in accordance with the data word length of the instruction, and to, when the data word length of the preceding instruction is longer than the data word length of the following instruction, determine the presence/absence of register interference between at least one array element to be processed in the non-leading cycle of the preceding instruction and the array element to be processed in the leading cycle of the following instruction, and to adjust the issue timing of the following instruction based on the determination result of the register interference. <P>COPYRIGHT: (C)2012,JPO&INPIT |
