发明名称 |
REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER |
摘要 |
Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.
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申请公布号 |
US2012132921(A1) |
申请公布日期 |
2012.05.31 |
申请号 |
US20100956145 |
申请日期 |
2010.11.30 |
申请人 |
TAWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN CHI-MING;YU CHUNG-YI;TSAI CHIA-SHIUNG;HWANG HO-YUNG DAVID |
分类号 |
H01L29/20;H01L21/18;H01L21/20 |
主分类号 |
H01L29/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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