3T HIGH DENSITY NVDRAM CELL

摘要

A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges. The single transistor may comprise a SONOS transistor or a Floating-Gate transistor. A method of operating a combined volatile and nonvolatile memory circuit may comprise causing a first charge representing a nonvolatile bit to be stored in a charge trapping region of a transistor; and causing a second charge representing a volatile bit to be stored outside the charge trapping region of the transistor. A device may comprise a processor coupled to interact with a memory system, the memory system comprising an array of memory cells each storing a single volatile bit and a single nonvolatile bit, each cell employing a single transistor to store the volatile bit and to store the nonvolatile bit.