Multi-level memory device

摘要

The device (100) has a back gate (106) including a portion (108) of a thin dielectric layer, and a semiconductor nanobeam (110) arranged on the portion of thin dielectric layer. A portion of dielectric layer (112) covers the nanobeam. A storage layer (114) performs storage of electrical charges, and covers the dielectric layer. A portion (116) of silicon dioxide layer covers the storage layer that performs the storage of electrical charges. A front gate includes a portion (120) of electrically conductive polycrystalline silicon covering the portion of silicon dioxide layer. An independent claim is also included for a method for programming and reading in a memory device.