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发明名称
Circuit logique et son mode d'utilisation dans des compteurs d'intervalles de temps à interpolation
摘要
申请公布号
FR1468727(A)
申请公布日期
1967.02.10
申请号
FR19650022445
申请日期
1965.06.25
申请人
ABLE RESEARCH LAB
发明人
ROSENBERRY WILLIAM KENNETH
分类号
G04F10/04
主分类号
G04F10/04
代理机构
代理人
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地址
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