发明名称 |
SIGNAL PROCESSING SYSTEM, INTEGRATED CIRCUIT COMPRISING BUFFER CONTROL LOGIC AND METHOD THEREFOR |
摘要 |
A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered. |
申请公布号 |
EP2457168(A1) |
申请公布日期 |
2012.05.30 |
申请号 |
EP20090847522 |
申请日期 |
2009.07.20 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ROBERTSON, ALISTAIR;CIRCELLO, JOSEPH;MAIOLANI, MARK |
分类号 |
G06F13/16;G06F5/00;G06F9/38;G06F12/08;G06F12/12 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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