Parallel power inverter motor drive system

摘要

Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.