| 摘要 |
A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The common PFPORT secures an entry when the prefetch request loaded from the PFPORT into a L2 pipeline processing unit fails to be completed. The uncompleted prefetch request is loaded again from the common PFPORT to the L2 pipeline processing unit.
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