发明名称 |
Hierarchical bus structure and memory access protocol for multiprocessor systems |
摘要 |
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus. |
申请公布号 |
US8190803(B2) |
申请公布日期 |
2012.05.29 |
申请号 |
US20080341778 |
申请日期 |
2008.12.22 |
申请人 |
HOBSON RICHARD F.;RESSL BILL;DYCK ALLAN R.;SCHISM ELECTRONICS, L.L.C. |
发明人 |
HOBSON RICHARD F.;RESSL BILL;DYCK ALLAN R. |
分类号 |
G06F13/368;G06F3/00;G06F13/00;G06F13/362;G06F13/372;G06F15/167 |
主分类号 |
G06F13/368 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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