发明名称 Write combining cache with pipelined synchronization
摘要 Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with said memory, calculating one or more matches between said events and said data stored in one or more cache-lines of said cache, storing event time stamps of events associated with said matches, generating one or more priority values based on said event time stamps, concurrently transmitting said data to said memory based on said priority values.
申请公布号 US8190826(B2) 申请公布日期 2012.05.29
申请号 US20080128149 申请日期 2008.05.28
申请人 LEFEBVRE LAURENT;MANTOR MICHAEL;HANKINSON ROBERT;ADVANCED MICRO DEVICES, INC. 发明人 LEFEBVRE LAURENT;MANTOR MICHAEL;HANKINSON ROBERT
分类号 G06F12/00;G06F13/00;G06F13/28 主分类号 G06F12/00
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