PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY
摘要
An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
申请公布号
WO2012067871(A2)
申请公布日期
2012.05.24
申请号
WO2011US59529
申请日期
2011.11.07
申请人
INTEL CORPORATION;SUNDARAM, RAJESH;KAU, DERCHANG;ZIMMERMAN, DAVID J.
发明人
SUNDARAM, RAJESH;KAU, DERCHANG;ZIMMERMAN, DAVID J.