发明名称 DESIGN DEVICE AND DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a design device for a semiconductor integrated circuit that attains improved quality and a low cost by inserting a minimum number into a place effective in improvement of fault detection. <P>SOLUTION: An inspection point is inserted by using a net list of a logic circuit, and information on a logic gate whose fault cannot be detected in the logic circuit or information on a logic gate whose fault detection processing is discontinued. At a place where fault detection is impossible, an inspection point is inserted into undetected logic present at a position where the number of logic stages is least when viewed from a fault detection trouble place as a logic gate, a terminal or a hardware macro impeding fault detection. At a place where the fault detection processing has been discontinued, an inspection point is inserted into a signal line connected to an undetected place at a position where the number of logic stages from an output terminal of a flip-flop transmitting a signal to a combination circuit is least in a logic path between the flip-flop transmitting the signal to the combination circuit and a flip-flop receiving the signal output from the combination circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012099028(A) 申请公布日期 2012.05.24
申请号 JP20100247903 申请日期 2010.11.04
申请人 PANASONIC CORP 发明人 KAMIHIRA TSUNETOMO;OKAWA TSUTOMU;YAMAJI AKIHIRO;SEKIGUCHI HIROYUKI;NAGAI SHINTARO;SAKAI YASUNAO;KUROKAWA NATSUKI;KOBAYASHI TAKUYA;SHIODA RYOJI
分类号 G06F17/50 主分类号 G06F17/50
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