发明名称 |
Method for Reducing the Range in Resistivities of Semiconductor Crystalline Sheets Grown in a Multi-Lane Furnace |
摘要 |
A method for reducing the range in resistivities of semiconductor crystalline sheets produced in a multi-lane growth furnace. A furnace for growing crystalline sheets is provided that includes a crucible with a material introduction region and a crystal growth region including a plurality of crystal sheet growth lanes. The crucible is configured to produce a generally one directional flow of material from the material introduction region toward the crystal sheet growth lane farthest from the material introduction region. Silicon doped with both a p-type dopant and an n-type dopant in greater than trace amounts is introduced into the material introduction region. The doped silicon forms a molten substance in the crucible called a melt. Crystalline sheets are formed from the melt at each growth lane in the crystal growth region. Co-doping the silicon feedstock can reduce the variation in resistivities among the crystalline sheets formed in each lane. |
申请公布号 |
US2012125254(A1) |
申请公布日期 |
2012.05.24 |
申请号 |
US20100952288 |
申请日期 |
2010.11.23 |
申请人 |
KERNAN BRIAN D.;TARNOWSKI GARY J.;HUANG WEIDONG;REITSMA SCOTT;RICHARDSON CHRISTINE;EVERGREEN SOLAR, INC. |
发明人 |
KERNAN BRIAN D.;TARNOWSKI GARY J.;HUANG WEIDONG;REITSMA SCOTT;RICHARDSON CHRISTINE |
分类号 |
C30B11/02 |
主分类号 |
C30B11/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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