发明名称
摘要 <P>PROBLEM TO BE SOLVED: To achieve an arithmetic configuration that makes analysis based on transient transition difficult and has high resistance, for example, to DPA attack. <P>SOLUTION: An arithmetic unit applies a logic circuit for performing data conversion processing, such as the nonlinear conversion processing and linear conversion processing of an input bit, and generates an output bit. In this case, input bit transition processing that is the switching processing of the input bit to the logic circuit is executed in a precharge phase, where the output of the logic circuit is maintained at a fixed value, and transition to an evaluation phase is made after input bit transition processing is completed for performing the generation processing of the output bit based on the data conversion processing, thus making difficult the analysis based on the transient transition occurring in the input bit transition processing, and achieving the arithmetic unit having high resistance, for example, to the DPA (Differential Power Analysis) attack. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP4935229(B2) 申请公布日期 2012.05.23
申请号 JP20060211189 申请日期 2006.08.02
申请人 发明人
分类号 H04L9/10;G06F7/00 主分类号 H04L9/10
代理机构 代理人
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