发明名称 Cache memory controller and cache memory controlling method
摘要 In a separating device that separates a processor configured to perform process by using data recorded in a cache memory connected to the processor, a stopping unit, upon receiving a processor separation request, stops the processor from performing a new process; and a separation executing unit, upon completion of process being performed by the processor, separates the processor after invalidating the data recorded in the cache memory.
申请公布号 US8185699(B2) 申请公布日期 2012.05.22
申请号 US20080222231 申请日期 2008.08.05
申请人 ENDO KUMIKO;SAKURAI HITOSHI;FUJITSU LIMITED 发明人 ENDO KUMIKO;SAKURAI HITOSHI
分类号 G06F12/00;G06F13/00 主分类号 G06F12/00
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