发明名称 |
Processor for performing multiply-add operations on packed data |
摘要 |
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. |
申请公布号 |
US8185571(B2) |
申请公布日期 |
2012.05.22 |
申请号 |
US20090409275 |
申请日期 |
2009.03.23 |
申请人 |
PELEG ALEXANDER D.;MITTAL MILLIND;MENNEMEIER LARRY M.;EITAN BENNY;DULONG CAROLE;KOWASHI EIICHI;WITT WOLF;INTEL CORPORATION |
发明人 |
PELEG ALEXANDER D.;MITTAL MILLIND;MENNEMEIER LARRY M.;EITAN BENNY;DULONG CAROLE;KOWASHI EIICHI;WITT WOLF |
分类号 |
G06F7/38;G06F7/48;G06F7/52;G06F7/533;G06F7/544;G06F9/302;G06F15/78;G06F17/14;G06F17/16;G06T1/20 |
主分类号 |
G06F7/38 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|