| 摘要 |
PURPOSE: A digital logic circuit with a dynamic logic gate is provided to reduce gate delay without adopting a keeper circuit for a dynamic logic gate. CONSTITUTION: A digital logic gate includes an N stage dynamic logic gate(50) and a Flip Flop(140). The N stage dynamic logic gate includes dynamic logic gates(10,11,14), which is sub-connected to an N stage, to successively logic-gating a plurality of first N input data in response to a first clock signal and second to N clock signals. The Flip Flop includes a delay unit which generates a D type Flip-Flop and a delay clock for latching the gating output of the N stage dynamic logic gate. The dynamic logic gate includes a pre-charge transistor, a discharge transistor, and a full down network.
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