发明名称 Method and apparatus for power reduction for interconnect links
摘要 A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.
申请公布号 US8185072(B2) 申请公布日期 2012.05.22
申请号 US20070690759 申请日期 2007.03.23
申请人 HUNSAKER MIKAL;VADIVELU KARTHI R.;INTEL CORPORATION 发明人 HUNSAKER MIKAL;VADIVELU KARTHI R.
分类号 H04B1/10 主分类号 H04B1/10
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