发明名称 |
Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering |
摘要 |
A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
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申请公布号 |
US8183640(B2) |
申请公布日期 |
2012.05.22 |
申请号 |
US20090502239 |
申请日期 |
2009.07.14 |
申请人 |
HUNG WEN-HAN;CHEN TSAI-FU;TING SHYH-FANN;HUANG CHENG-TUNG;LEE KUN-HSIEN;LO TA-KANG;CHENG TZYY-MING;UNITED MICROELECTRONICS CORP. |
发明人 |
HUNG WEN-HAN;CHEN TSAI-FU;TING SHYH-FANN;HUANG CHENG-TUNG;LEE KUN-HSIEN;LO TA-KANG;CHENG TZYY-MING |
分类号 |
H01L29/76;H01L29/94 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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