发明名称 |
Selective powering of a BHT in a processor having variable length instructions |
摘要 |
In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.
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申请公布号 |
US8185725(B2) |
申请公布日期 |
2012.05.22 |
申请号 |
US20090612860 |
申请日期 |
2009.11.05 |
申请人 |
STEMPEL BRIAN MICHAEL;SMITH RODNEY WAYNE;QUALCOMM INCORPORATED |
发明人 |
STEMPEL BRIAN MICHAEL;SMITH RODNEY WAYNE |
分类号 |
G06F7/38;G06F9/00;G06F9/44;G06F15/00 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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