发明名称 |
Single event upset error detection within an integrated circuit |
摘要 |
An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8. |
申请公布号 |
US8185812(B2) |
申请公布日期 |
2012.05.22 |
申请号 |
US20060636716 |
申请日期 |
2006.12.11 |
申请人 |
DAS SHIDHARTHA;BLAAUW DAVID THEODORE;BULL DAVID MICHAEL;ARM LIMITED;THE REGENTS OF THE UNIVERSITY OF MICHIGAN |
发明人 |
DAS SHIDHARTHA;BLAAUW DAVID THEODORE;BULL DAVID MICHAEL |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|