发明名称 SUB-PIXEL GENERATION FOR HIGH SPEED COLOR LASER PRINTERS USING A CLAMPING TECHNIQUE FOR PLL (PHASE LOCKED LOOP) CIRCUITRY
摘要 Methods and apparatus for optimizing the phase lock loop circuitry of subpixel clock generators for situations where frequent switching between different system printing speeds, and hence clock frequencies are required. An optimizing circuit is associated with a sub-pixel clock generator for clamping an input voltage to a voltage controlled oscillator controlling clock frequency between a desired range. The clamping circuitry comprises a comparator for detecting when the voltage has moved out of the desired range and then charges or discharges a loop filter circuit controlling the input voltage to the VCO to keep the input voltage within the desired range.
申请公布号 CA2618401(C) 申请公布日期 2012.05.22
申请号 CA20082618401 申请日期 2008.01.16
申请人 XEROX CORPORATION 发明人 YAZDY, MOSTAFA R.
分类号 G03G13/05;G03G15/00;G03G15/05 主分类号 G03G13/05
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