| 摘要 |
<p>In a level shift circuit capable of providing a preferable operation with short delay time even when low voltage is established from a low voltage source, for example, when an input signal (IN) is state-changed from a high (VDD) level to a low level, a node (W2) pre-charged at a high (VDD3) level is discharged to ground (VSS) via a discharge circuit (N2) and the potential is dropped, the potential drop is sent to a latch circuit (LA) and the output of the latch circuit (LA) is sent to an output circuit (OC). Further, a reversed signal of the node (W2) is inputted into the output circuit (OC) while bypassing the latch circuit (LA). As such, the output circuit (OC) at an early stage starts the operation prior to the operation based on the output of the latch circuit (LA). Thus, even when a normal voltage is established where the voltage of the low voltage source is established as the normal voltage, a preferable level shift is performed having an output signal with reduced delay time.</p> |
