FEEDBACK SCAN ISOLATION AND SCAN BYPASS ARCHITECTURE
摘要
<p>A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.</p>
申请公布号
WO2012065064(A1)
申请公布日期
2012.05.18
申请号
WO2011US60372
申请日期
2011.11.11
申请人
QUALCOMM INCORPORATED;POLICKE, PAUL F.;KIM, HONG S.;BASSETT, PAUL DOUGLAS
发明人
POLICKE, PAUL F.;KIM, HONG S.;BASSETT, PAUL DOUGLAS