| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an error correction device capable of reducing an access amount to an external memory even while suppressing an increase in a circuit scale due to an increase in a built-in memory capacity. <P>SOLUTION: A descramble circuit 20 includes an EOR circuit 21 for receiving scramble data sDu from a built-in memory in which an ECC cluster is divided from a demodulator circuit and stored. The descramble circuit 20 includes: a one-shift computing element 24 for shifting an inputted scramble value for one byte according to a generating function Φ(x) to generate a new scramble value, and a 209 shift computing element 25 for shifting the inputted scramble value for 209 bytes according to the generating function Φ(x) to generate a new scramble value. The descramble circuit 20 includes a selection circuit 28 and a selector 27 for selecting a scramble value to be outputted to the EOR circuit 21 in accordance with a processing order during scramble processing of the scramble data sDu to be inputted to the EOR circuit 21. <P>COPYRIGHT: (C)2012,JPO&INPIT |
