| 摘要 |
A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect. If the condition prediction is incorrect, then the condition resolution circuitry flushes any micro-operation instructions associated with the conditional program instruction from the processing circuitry, changes the condition prediction to a new prediction and triggers the redecoding of the conditional program instruction in accordance with the new condition prediction.
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