| 摘要 |
In a digital PLL frequency synthesizer, after lock detection, first oscillating signal phase information is switched to second oscillating signal phase information by an estimation section based on previous oscillating signal phase information and a phase difference. As a result, the first oscillating signal phase information which has a risk of an error in the normal state (locked state) is not used. In addition, a conventional high-speed latch circuit for reclocking is not required. As a result, power consumption can be reduced, compared to the conventional art, while reducing or avoiding a degradation in phase-noise characteristics.
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