发明名称 Fuse Circuit
摘要 A fuse circuit comprises a fuse set and an enable circuit. The enable circuit is configured to receive a test mode enable signal and a power up signal to generate an enable signal and a voltage level to the fuse set for indicating whether an external supply voltage reaches a predetermined value and whether a test mode is enabled. In particular, an output signal of the fuse set is constant in the test mode, regardless of whether a fuse in the fuse set is blown or not.
申请公布号 US2012119820(A1) 申请公布日期 2012.05.17
申请号 US20100946894 申请日期 2010.11.16
申请人 HUANG PEI JEY;ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. 发明人 HUANG PEI JEY
分类号 H01H37/02 主分类号 H01H37/02
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