| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a memory capacity necessary for analyzing an address of a defective memory cell. <P>SOLUTION: Multiple memory cells are sequentially tested and error pattern information is updated based on a relative arrangement relation of multiple defective memory cells each time a defective memory cell is detected by the test, and error address information is updated based on at least a part of the addresses of the multiple defective memory cells. Since a memory capacity of a memory for analysis can be greatly reduced, the memory for analysis itself can be mounted in a semiconductor device, which eliminates necessity of providing a memory for analysis on an external tester. <P>COPYRIGHT: (C)2012,JPO&INPIT |
