| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a pattern insertion circuit for OOR testing for causing disturbance of LM, for confirming that a reception side correctly detects and releases OOR. <P>SOLUTION: The pattern insertion circuit for OOR testing includes: a code inversion part 32 which, with OTU3 frame data DT<SB POS="POST">0</SB>-DT<SB POS="POST">3</SB>being inputted, inverts one bit (a<SB POS="POST">0</SB>) among the LM arranged at bottom two bits (a<SB POS="POST">1</SB>a<SB POS="POST">0</SB>) being the representation of MFAS in binary format, to (r<SB POS="POST">0</SB>); an alarm pattern generating part 33 which replaces the other bit (a<SB POS="POST">1</SB>) of the LM with the data (b<SB POS="POST">1</SB>) of code (0) or code (1) so that repetition of identical code is four times or less, and (r<SB POS="POST">0</SB>) from the code inversion part 32 is arranged at one bit, for generating a pattern (b<SB POS="POST">1</SB>r<SB POS="POST">0</SB>) for OOR testing of 2 bit; and an alarm pattern insertion part 34 which replaces an LM of arbitrary lane with the pattern for ORR testing that is generated by the alarm pattern generating part 33. <P>COPYRIGHT: (C)2012,JPO&INPIT |
