| 摘要 |
A translation lookaside buffer (TLB) includes a data array including memory storage cells arranged to form a number of entries. Each entry may store a translated physical address. The data array also includes an integrated multiplexer that may be coupled to an output of the data array. The integrated multiplexer may include a respective first bit select transistor that may be coupled between an output of each of at least some of the memory storage cells and the output of the data array. In addition, the integrated multiplexer may bit-wise select as the output of the data array, one of the translated physical address or another address provided to the data array from external to the TLB in response to a given entry being accessed.
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