| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a multi-modulus divider (MMD) that implements low jitter and reduces power consumption. <P>SOLUTION: The MMD includes a chain of MDSs. Each MDS (DIV23) divides an input signal by either two or three, and outputs the result as an output signal. Each MDS (DIV23) responds to a modulus control signal that controls whether it divides by two or three. A retiming circuit 149 outputs SOUT. The modulus control signal (MC1B) of the first MDS (DIV23) of the chain is used to place the retiming circuit 149 into a first state. The output signal O5 of the fifth MDS (DIV23) of the chain is used to place the retiming circuit 149 into a second state. <P>COPYRIGHT: (C)2012,JPO&INPIT |
