| 摘要 |
A circuit for preventing increase of a core voltage is provided to secure a stable operation and to implement a low power memory device, by reducing current consumption caused as an over-driving and a release operation are performed at the same time. An over driving signal delay part(120) generates a first enable signal in response to a number of bank signals, and generates a second enable signal by delaying the first enable signal, and generates a third enable signal in response to the second enable signal. An enable signal generation part(140) generates a release stop signal in response to the first and second enable signals, and generates a release enable signal in response to the release stop signal and the third enable signal. A voltage comparison part generates a driving signal by comparing a core voltage with a reference voltage in response to the release enable signal. A switching part(170,180) controls the core voltage in response to the driving signal and the release enable signal.
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