发明名称 System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
摘要 A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a first set of lane processing units (LPUs) configured to perform data-parallel operations, where each LPU performs a set of operations, and each LPU uses a different set of data for the set of operations, and each LPU within the first set of LPUs uses a different set of data for the set of operations. The second LPE includes a second set of LPUs configured to perform task-parallel operations, where each LPU performs a different set of operations. A processing control engine (PCE) is configured to distribute instructions and data to the first LPE and the second LPE. Advantageously, data parallel operations and task parallel operations are able to be performed on the same processor simultaneously.
申请公布号 US8180998(B1) 申请公布日期 2012.05.15
申请号 US20080208231 申请日期 2008.09.10
申请人 MAHER MONIER;LAMB CHRISTOPHER;PATEL SANJAY J.;HSU PETER;NVIDIA CORPORATION 发明人 MAHER MONIER;LAMB CHRISTOPHER;PATEL SANJAY J.;HSU PETER
分类号 G06F15/16 主分类号 G06F15/16
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